1. Field of the Invention
The present invention relates to a MISFET (insulated gate field-effect transistor) circuit. More particularly, it relates to a MISFET circuit which provides high-speed operation in an MIS type semiconductor memory device.
2. Description of the Prior Art
The chip of an MIS memory of high density is based on a memory cell system which exploits the fact that, during operation, the input current of a MISFET is substantially zero. Charges accumulated in a cell decrease gradually due to leakage at a junction associated with elements for access and for sense operations. In such a cell, therefore, it is necessary to periodically perform an access operation for refreshing the accumulated charge. That is, a dynamic operation is carried out.
The dynamic memory cell generally utilizes 3-element type and 4-element type cells.
In the cell of the 3-element type, as shown in FIG. 3, information is accumulated as a charge on capacitor C.sub.1 at the gate of a MISFET M.sub.1 which is an active element of comparatively large size. Upon access to the cell, at the beginning of a cycle, the voltages at a terminal D and at terminal B are preestablished at a voltage nearly equal to the supply voltage V.sub.DD. When a read select line is subsequently enabled MISFET M.sub.2, the transmitting information, becomes conductive. If the voltage of the gate of the MISFET M.sub.1 is greater than the threshold voltage, the MISFET M.sub.1 will conduct, and the voltage level at terminal B will drop to a voltage near source voltage V.sub.SS. If the gate voltage of the MISFET M.sub.1 (charge on the gate capacitance C.sub.1) is insufficient and the MISFET M.sub.1 cannot be rendered conductive, the terminal B will remain preset at the supply voltage V.sub.DD. The state of the column B is sensed by an on-chip amplifier, to thereby detect information.
FIG. 4 shows a dynamic memory cell of the 4-element type. Four active elements are connected forming a latch circuit similarly to flip-flops which are used in a static memory. This cell, however, is dynamic, since no load element is employed.
Information is stored in the gate capacitors C.sub.4 and C.sub.5 of MISFETs M.sub.4 and M.sub.5. As two elements are used, both normal information and reverse information are obtained by internal detector circuits.
The information is acquired through information transmitting MISFETs M.sub.6 and M.sub.7 substantially in the same way as in the case of the 3-element type. At the beginning of a cycle, the voltages at terminal D and terminal D are preset at a voltage near the supply voltage V.sub.DD. When the row is subsequently selected, the information transmitting MISFETs M.sub.6 and M.sub.7 conduct. If a charge has been accumulated on the gate capacitor C.sub.4, the MISFET M.sub.4 will conduct and the voltage at terminal D will therefore drop to a voltage near source voltage V.sub.SS. The voltage at the other terminal D remains preset since MISFET M.sub.5 is nonconductive.
Although the memory of this element type produces the two forms of output information D and D, actually the information of either the terminal D or the terminal D may be used as the read-out signal.
The above memories of the dynamic type have a small number of elements and, moreover, have a low power dissipation, since no DC current is caused to flow. They are, therefore, very convenient for constructing a memory device of large capacity.
On the other hand, the dynamic type memory cell is so formed as to make the best use of the high integration density being one of its features, and hence, each MISFET is inevitably made small. This leads to the disadvantage that the output impedance of each MISFET is high, to render to operation of the device slow. More specifically, as previously stated, the operation of the dynamic type memories is such that, after determining whether or not charges preestablished in the line of the columns are discharged by the storing information of the memory cell, information is read out. The access time is therefore determined from the instant of designation of the memory cell to the read-out of information.
Since the impedance of the MISFET of the memory cell which constitutes the discharging path is high, as described above, the time necessary for discharge or the access time is long.